2008年10月6日 Add-half (Gate-live Modeling)

Design a verilog model of a half adder and write a testbench to verify the designed verilog model.

P.9(課本第九頁)

module add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule