2008年11月24日

&2.5 Glitches and Hazard

The output of a combinational circuit make a transition even though the logical
values applied at its inputs do not imply a change.

These unwated switching transients are called "glitches"

If a circuit has a hazard it could exhibit a glitch under certain conditions.

2008年10月13號 Add-full

2008年10月13號 Add-half (Behavoral Modeling)

module add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
reg sum,c_out;

always
begin
sum=a+b;
c_out=a*b;
end
endmodule

2008年10月6日 Add-half (Gate-live Modeling)

Design a verilog model of a half adder and write a testbench to verify the designed verilog model.

P.9(課本第九頁)

module add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule

2008年9月22日

module top;
wire a,b;
reg c;

system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a&b;

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;

always
begin
# (PERIOD/2) clk = ~clk;
# (PERIOD/2) clk = ~clk;
end

always@(posedge clk)
if ($time>1000)
# (PERIOD-1)$stop;

endmodule

SynaptiCAD 使用簡介

http://www.dyu.edu.tw/~cschen/CODA/doc/syncad.doc

http://www.dyu.edu.tw/~cschen/Verilog%20Computer%20Design/SynaptiCAD.exe

2008年9月15號

2008/09/15：

課程Blog：http://dyu9502.blogspot.com

參考書籍："Modeling, Synthesis, and Rapid Prototyping with the VERILOG HDL"
by Michael D. Ciletti
Paperback: 724 pages
Publisher: Prentice Hall; Bk&CD-Rom edition (March 18, 1999)
Language: English
ISBN-10: 0139773983

成績比重：平時40% , 上機30% , 期末30%